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STV9425 - STV9425B STV9426
MULTISYNC ON-SCREEN DISPLAY FOR MONITOR
. . . . . . . . . . . . . .
CMOS SINGLE CHIP OSD FOR MONITOR BUILT IN 1 KBYTE RAM HOLDING : - PAGES' DESCRIPTORS - CHARACTER CODES - USER DEFINABLE CHARACTERS 128 ALPHANUMERIC CHARACTERS OR GRAPHIC SYMBOLS IN INTERNAL ROM (12 x 18 DOT MATRIX) UP TO 26 USER DEFINABLE CHARACTERS INTERNAL HORIZONTAL PLL (15 TO 120kHz) PROGRAMMABLE VERTICAL HEIGHT OF CHARACTER WITH A SLICE INTERPOLATOR TO MEET MULTI-SYNCH REQUIREMENTS PROGRAMMABLE VERTICAL AND HORIZONTAL POSITIONING FLEXIBLE SCREEN DESCRIPTION CHARACTER BY CHARACTER COLOR SELECTION (UP TO 8 DIFFERENT COLORS) PROGRAMMABLE BACKGROUND (COLOR, TRANSPARENT OR WITH SHADOWING) 50MHz MAXIMUM PIXEL CLOCK 2-WIRES ASYNCHRONOUS SERIAL MCU INTERFACE (I2C PROTOCOL) 8 x 8 BITS PWM DAC OUTPUTS (STV9425) 4 x 8 BITS PWM DAC OUTPUTS (STV9425B) SINGLE POSITIVE 5V SUPPLY
8 x 8 bits or 4 x 8 bits PWM DAC are available to provide DC voltage control to other peripherals. The STV9425/25B/26provides the user an easy to use and cost effective solution to display alphanumeric or graphic information on monitor screen.
SHRINK24 (Plastic Package) ORDER CODES : STV9425 - STV9425B
DESCRIPTION TheSTV9425/25B/26is an ON SCREEN DISPLAY for monitor. It is built as a slave peripheral connected to a host MCU via a serial I2C bus. It includes a display memory, controls all the display attributes and generates pixels from the data read in its on chip memory. The line PLL and a special slice interpolator allow to have a display aspect which does not depend on the line and frame frequencies. I 2C interface allows MCU to make transparent internal access to prepare the next pages during the display of the current page. Toggle from one page to another by programming only one register.
December 1997
DIP16 (Plastic Package) ORDER CODE : STV9426
1/15
STV9425 - STV9425B - STV9426
PIN CONNECTIONS
SDIP24 (STV9425)
PWM0 PWM1 FBLK VSYNC HSYNC VDD PXCK CKOUT XTAL OUT XTAL IN PWM2 PWM3 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 PWM7 PWM6 TEST B G R GND RESET SDA SCL PWM5 PWM4 RESERVED P WM1 FBLK VSYNC HS YNC VDD P XCK CKOUT XTAL OUT XTAL IN P WM2 RESERVED
SDIP24 (STV9425B)
1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 RES ERVED P WM6 TE S T B G R GND RES ET S DA S CL P WM5 RES ERVED FBLK V-SYNC H-SYNC V DD PXCK CKOUT XTAL OUT XTAL IN
DIP16 (STV9426)
1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 TEST B G R GND RESET SDA SCL
9425-01.EPS /9425B-01.EPS/ 9426-01.EPS 9425-01.TBL
PIN DESCRIPTION
Symbol PWM0 PWM1 FBLK V-SYNC H-SYNC VDD PXCK CKOUT XTAL OUT XTAL IN PWM2 PWM3 PWM4 PWM5 SCL SDA RESET GND R G B TEST PWM6 PWM7 Pin Number SDIP24 1* 2 3 4 5 6 7 8 9 10 11 12 * 13 * 14 15 16 17 18 19 20 21 22 23 24 * DIP16 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 O O O I I S O O O I O O O O I I/O I S O O O I O O DAC0 Output DAC1 Output Fast Blanking Output Vertical Sync Input Horizontal Sync Input +5V Supply Pixel Frequency Output Clock Output Crystal Output Crystal or Clock Input DAC2 Output DAC3 Output DAC4 Output DAC5 Output Serial Clock Serial Input/Output Data Reset Input (Active Low) Ground Red Output Green Output Blue Output Reserved (grounded in Normal Operation) DAC6 Output DAC7 Output I/O Description
* Reserved with STV9425B (not to be connected)
2/15
STV9425 - STV9425B - STV9426
BLOCK DIAGRAMS STV9425
XTAL IN 10 CKOUT 8 HS YNC 5 XTAL OUT 9 PXCK 7 VDD 6 TEST 22 24 P WM7 * HORIZONTAL DIGITAL PLL 4K ROM (128 chara cte rs) 1K RAM Pa ge Descriptors + Use r Defined Cha r. PWM 23 P WM6 14 P WM5 13 P WM4 * 12 P WM3 * 11 P WM2 2 P WM1 1 P WM0 *
9425-02.EPS
Addre ss/Data
VSYNC 4 RES ET 17
DISP LAY CONTROLLER
I C BUS INTERFACE
2
1 9 2 0 21 R G B
3 FBLK
18 GND
15 SCL
16 SDA
S TV94 25/25B
* Res erve d with STV9425B
STV9426
XTAL XTAL IN OUT P XCK
8 7 5 VDD 4
TEST
16
CKOUT 6 HS YNC 3
HOR IZONTAL DIGITALP LL
4K ROM (128 cha ra cte rs )
1K RAM P age De s criptors + Us e r De fined Char.
Addre s s /Da ta
VSYNC 2 RESET 11
DISP LAY CONTROLLER
I C BUS INTERFACE
2
S TV9426
13 14 15
R
G
B
1 FBLK
12 GND
9 SCL
10
SDA
3/15
9426-02.EPS
STV9425 - STV9425B - STV9426
ABSOLUTE MAXIMUM RATINGS
Symbol V DD V IN Toper Tstg Supply Voltage Input Voltage Operating Ambient Temperature Storage Temperature Parameter Value -0.3, +7.0 -0.3, +7.0 0, +70 -40, +125 Unit V V C C
9425-02.TBL 9425-03.TBL
ELECTRICAL CHARACTERISTICS (VDD = 5V, VSS = 0V, T A = 0 to 70C, F XTAL = 8 to 15MHz, TEST = 0 V, unless otherwise specified)
Symbol SUPPLY V DD IDD INPUTS SCL, SDA, TEST, RESET, V-SYNC and H-SYNC VIL V IH IIL OUTPUTS R, G, B, FBLK, SDA, CKOUT, PXCK and PWMi (i = 0 to 7) VOL VOH Output Low Voltage (IOL = 1.6mA) Output High Voltage (IOL = -0.1mA) 0 0.8V DD 0.4 VDD V V Input Low Voltage Input High Voltage Input Leakage Current 0.8V DD -20 +20 0.8 V V A Supply Voltage Supply Current 4.75 5 50 5.25 70 V mA Parameter Min. Typ. Max. Unit
For R, G, B and FBLK outputs, see Figure 1.
Figure 1 : Typical R, G, B Outputs Characteristics
5 VOL , VOH (V)
VOH 2.5
VOL 0 10 -5 10 -4 10 -3 10 -2 10 -1
9425-17.EPS
I (A)
4/15
STV9425 - STV9425B - STV9426
TIMINGS
Symbol Parameter Min. Typ. Max. Unit OSCILATOR INPUT : XTI (see Figure 2) TWH T WL FXTAL FPXL RESET TRES Reset Low Level Pulse 4 s Clock High Level Clock Low Level Clock Frequency Pixel Frequency 20 20 TBD 15 50 ns ns MHz MHz
R, G, B, FBLK (CLOAD = 30pF) TRISE TFALL TSKEW
2
Rise Time (Note 1) Fall Time (Note 1) Skew between R, G, B, FBLK (Note 1)
5 5 5
ns ns ns
I C INTERFACE : SDA AND SCL (see Figure 3) FSCL TBUF THDS TSUP TLOW THIGH THDAT TSUDAT TF TR SCL Clock Frequency Time the bus must be free between 2 access Hold Time for Start Condition Set up Time for Stop Condition The Low Period of Clock The High Period of Clock Hold Time Data Set up Time Data Fall Time of SDA Rise Time of Both SCL and SDA 0 500 500 500 400 400 0 375 20 Depend on the pull-up resistor and the load capacitance 1 MHz ns ns ns ns ns ns ns
9425-04.TBL 9425-04.AI
ns
Note 1 : These parameters are not tested on each unit. They are measured during our internal qualification procedure which includes characterization on batches comming from corners of our processes and also temperature characterizat ion.
Figure 2
Figure 3
STOP START DATA THDAT STOP TBUF
TWL
SDA
XTI TWH
9425-03.AI
THDS SCL THIGH
TSUDAT
TSUP
TLOW
5/15
STV9425 - STV9425B - STV9426
FUNCTIONAL DESCRIPTION The STV9425/25B/26display processor operation is controlled by a host MCU via the I2C interface. It is fully programmab le through 16 internal read/write registers and performs all the display functions by generating pixels from data stored in its internal memory. After the page downloading from the MCU, the STV9425/25B/26 refreshes screen by its built in processor, without any MCU control (access).In addition, the host MCU has a direct access to the on chip 1Kbytes RAM during the display of the current page to make any update of its contents. With the STV9425/25B/26,a page displayed on the screen is made of several strips which can be of 2 types : spacing or character and which are described by a table of descriptors and character codes in RAM. Several pages can be downloaded at the same time in the RAM and the choice of the current display page is made by programming the CONTROL register. I - Serial Interface 2 The 2-wires serial interface is an I C interface. To 2 be connected to the I C bus, a device must own its slave address ; the slave address of t he STV9425/25B/26is BA (in hexadecimal).
A6 A5 A4 A3 A2 A1 A0 R/W 1 0 1 1 1 0 1
I.1 - Data Transfer in Write Mode T h e h o s t MCU ca n writ e d at a in t o t he STV9425/25B/26registers or RAM. To write data into the STV9425/25B/26, after a start, the MCU must send (Figure 3) : - First, the I2C address slave byte with a low level for the R/W bit, - The two bytes of the internal address where the MCU wants to write data(s), - The successive bytes of data(s). All bytes are sent MS bit first and the write data transfer is closed by a stop. I.2 - Data Transfer in Read Mode T h e h o st MCU c a n read d at a f ro m th e STV9425/25B/26registers, RAM or ROM. To read data from the STV9425/25B/26(Figure 4), 2 the MCU must send 2 different I C sequences.The 2 first oneis made of I C slave addressbyte with R/W bit at low level and the 2 internal address bytes. The second one is made of I2C slave address byte with R/W bit at high level and all the successive data bytes read at successive addresses starting from the initial address given by the first sequence.
Figure 3 : STV9425/25B/26/I2C Write Operation
SCL R/W SDA Start I2C Slave Address ACK
A7
A6
A5
A4
A3
A2
A1
A0 ACK
-
-
A13 A12
A11 A10
A9
A8 ACK
LSB Address
MSB Address
SCL
SDA
D7
D6
D5
D4
D3
D2
D1
D0 ACK
D7
D6
D5
D4
D3
D2
D1
D0 ACK
D7
D6
D5
D4
D3
D2
D1
D0 ACK Stop
9425-05.AI 9425-06.EPS
Data Byte 1
Data Byte 2
Data Byte n
Figure 4 : STV9425/25B/26/I2C Read Operation
SCL
R/W
SDA
A7
ACK
A6
A5
A4
A3
A2
A1
A0
ACK
-
-
A13 A12 A10 A10 A9
MSB Address
A8
ACK Stop
Start
I1 C
Slave Address
LSB Address
SCL
SDA
R/W Start I1 C Slave Address ACK
D7
D6
D5
D4
D3
D2
D1
D0
D7
D6
D5
D4
D3
D2
D1
D0
Data Byte 1
ACK
Data Byte n
ACK
Stop
6/15
STV9425 - STV9425B - STV9426
FUNCTIONAL DESCRIPTION (continued) I.3 - Addressing Space STV9425/25B/26 registers, RAM and ROM are mapped in a 16Kbytes addressing space. The mapping is the following :
0000 1024 bytes RAM 03FF 0400 Empty Space 1FFF 2000 32FF 3300 3FFF 3FF0 3FFF Character Generator ROM Empty Space Internal Registers Descriptors character codes user definable characters
DISPLAY CONTROL
3FF3 * OSD 0 FBK 0 FL1 0 FL0 0 P8 0 P7 0 P6 0
OSD FBK
: ON/OFF (if 0, R, G, B and FBLK are 0). : Fast blanking control : = 1 : FBLK = 1, forcing black where these is no display, = 0 : FBLK is active only during character display. FL[1:0] : Flashing mode : - 00 : No flashing. The character attribute is ignored, - 01 : 1/1 flashing (a duty cycle = 50%), - 10 : 1/3 flashing, - 11 : 3/1 flashing. P[8:6] : Address of the 1st descriptor of the current displayed pages. P[13:9] and P[5:0] = 0 ; up to 8 different pages can be stored in the RAM. LOCKING CONDITION TIME CONSTANT
3FF4 * FR 0 AS2 AS1 AS0 0 1 0 BS2 BS1 BS0 0 1 0
I.4 - Register Set LINE DURATION
3FF0 VSP HSP LD5 LD4 LD3 LD2 LD1 LD0 * 0 0 1 1 1 1 1 1
VSP
: V-SYNC active edge selection = 0 : falling egde, = 1 : rising edge HSP : H-SYNC active edge selection = 0 : falling egde, = 1 : rising edge LD[5:0] : LINE DURATION (number of pixel period per line divided by 12 ie. Unit = 12 pixel periods). HORIZONTAL DELAY
3FF1 DD7 DD6 DD5 DD4 DD3 DD2 DD1 DD0 * 0 0 0 0 1 0 0 0
: Free Running ; if = 1 PLL is disabled and the pixel frequency keeps its last value. AS[2:0] : P h a s e c o n s t ant du rin g lo ck ing conditions. BS[2:0] : Frequency constant during locking conditions. CAPTURE PROCESS TIME CONSTANT
3FF5 * AF2 0 AF1 1 AF0 1 BF2 0 BF1 1 BF0 1
FR
DD[7:0] : HORIZONTAL DISPLAY DELAY from the H-SYNC reference falling edge to the 1st pixel position of the character strips. Unit = 3 pixel periods. CHARACTERS HEIGHT
3FF2 * CH5 CH4 CH3 CH2 CH1 CH0 0 1 0 0 1 0
AF[2:0] : Phase constant during the capture process. BF[2:0] : Frequency constant during the capture process. INITIAL PIXEL PERIOD
3FF6 PP7 PP6 PP5 PP4 PP3 PP2 PP1 PP0 * 0 0 1 0 1 0 0 0
PP[7:0] : Value to initialize the pixel period of the PLL. FREQUENCY MULTIPLIER
3FF7 * FM3 FM2 FM1 FM0 1 0 1 0
CH[5:0] : HEIGHT of the character strips in scan lines. For each scan line, the number of the slice which is displayed is given by : SLICE-NUMBER =
SCAN-LINE-NUMBER x 18 round . CH[5:0]
SCAN-LINE-NUMBER = Number of the current scan line of the strip.
FM[3:0] : Frequency multiplier of the crystal frequency to reach the high frequency used by the PLL to derive the pixel frequency.
7/15
STV9425 - STV9425B - STV9426
FUNCTIONAL DESCRIPTION (continued) PULSE WIDTH MODULATOR 0
3FF8 * V07 V06 V05 V04 V03 V02 V01 V00 0 0 0 0 0
st
II - Descriptors SPACING
MSB LSB 0 SL7 SL6 SL5 SL4 SL3 SL2 SL1 SL0
0
0
0
V0[7:0] : Digital value of the 1 converter (Pin1). PULSE WIDTH MODULATOR 1
3FF9 *
PWM D to A
SL[7:0] : The number of the scan lines of the spacing strip (1 to 255). CHARACTER
MSB LSB 1 C7 DE C6 C5 ZY C4 C3 C2 C9 C1 C8 0 0 0 0
V17 V16 V15 V14 V13 V12 V11 V10 0 0 0 0 0
V1[7:0] : Digital value of the 2nd PWMDAC (Pin2). PULSE WIDTH MODULATOR 2
3FFA * V27 V26 V25 V24 V23 V22 V21 V20 0 0 0 0 0 0
rd
0
0
V2[7:0] : Digital value of the 3 (Pin11). PULSE WIDTH MODULATOR 3
3FFB *
PWM DAC
V37 V36 V35 V34 V33 V32 V31 V30 0 0 0 0 0 0
th
C[9:0] : The address of the first character code of the strip (even). DE : Display enable : - DE = 0, R = G = B = 0 and FBLK = FBK (display control register) on whole strip, - DE = 1, display of the characters. ZY : Zoom, ZY = 1 all the scan lines are repeated once. III - Code Format
MSB SET LSB CHARACTER NUMBER FL RF GF BF BK3 BK2 BK1 BK0
0
0
V3[7:0] : Digital value of the 4 (Pin12). PULSE WIDTH MODULATOR 4
3FFC *
PWM DAC
V47 V46 V45 V44 V43 V42 V41 V40 0 0 0 0 0 0
th
0
0
V4[7:0] : Digital value of the 5 (Pin13). PULSE WIDTH MODULATOR 5
3FFD *
PWM DAC
V57 V56 V55 V54 V53 V52 V51 V50 0 0 0 0 0 0 0 0
V5[7:0] : Digital value of the 6th PWM DAC (Pin14). PULSE WIDTH MODULATOR 6
3FFE * V67 V66 V65 V64 V63 V62 V61 V60 0 0 0 0 0 0 0 0
V6[7:0] : Digital value of the 7th PWM DAC (Pin23). PULSE WIDTH MODULATOR 7
3FFF * V77 V76 V75 V74 V73 V72 V71 V70 0 0 0 0 0 0 0 0
V7[7:0] : Digital value of the 8th PWM DAC (Pin24).
Note : * is power on reset value.
: The set CHARACTER NUMBER - If SET = 0 : ROM character, - If SET = 1 : * If CHARACTER NUMBER is 0 to 25, a user redefinable character (UDC) located in RAM at the address equal to : 38 x CHARACTER NUMBER, * If CHARACTER NUMBER is 26 to 63, space character, * If CHARACTER NUMBER>63, end of line. FL : Flashing attribute (the flashing mode is defined in the DISPLAY CONTROL register). RF, GF, BF: Foreground color. BK[3:0] : Background : - If BK3 = 0, BK[2:0] = background color R, G and B, - If BK3 = 1, shadowing : BK1 : horizontal shadowing. (if BK1 = 0, the background is transparent). BK2 and BK0 must be equal to 0.
SET
8/15
STV9425 - STV9425B - STV9426
FUNCTIONAL DESCRIPTION (continued) Figure 5 : Horizontal Timing
H-SYNC
R, G, B 0 1 2 3 n+1 n+2 n+3 n+4 LD - 1 LD 0 1
Character Period LD[5:0] Fixed DD[7:0] Given by number of characters of the strips
IV - Clock and Timing The whole timing is derived from the XTALIN and the SYNCHRO (horizontal and vertival) input frequencies. The XTALIN input frequency can be an external clock or a crystal signal thanks to XTALIN/XTALOUT pins. The value of this frequency can be chosen between 8 and 15MHz, it is available on the CKOUTpin and is used by the PLL to generate a pixel clock locked on the horizontal synchro input signal. IV.1 - Horizontal Timing (see Figure 5) The number of pixel periods is given by the LINE DURATION register and is equal to : [LD[5:0] + 1 ] x 12. (LD[5:0] : value of the LINE DURATION register). This value allows to choose the horizontal size of the characters. The horizontal left margin is given by the HORIZONTAL DELAY register and is equal to : [DD[7:0] + 8] x 3 x TPXCK (DD[7:0] : value of the DISPLAY DELAY register and T PXCK : pixel period). This value allows to choose the horizontal position of the characters on the screen. The value of DD[7:0] must be equal or greater than 4 (the minimum value of the horizontal delay is 36 x TPXCK = 3 character periods). The length of the active area, where R, G, B are different from 0, dependson the number of characters of the strips. IV.2 - D to A Timing The D to A converters of the STV9425/25B/26are pulse width modulater converter. The frequency of FXTAL the output signal is : 256 Vi[7:0] and the duty cycle is : per cent. 256
After a low pass filter, the average value of the Vi [7:0] VDD output is : 256 V - Display Control A screen is composed of successive scanlines gathered in several strips. Each strip is defined by a descriptor stored in memory. A table of descriptors allows screen composition and different tables can be stored in memory at thepage addresses(8 possible addresses).Two typesof strips are available : - Spacing strip : its descriptor (see II) gives the number of black (FBK = 1 in DISPLAYCONTROL register) or transparent (FBK = 0) lines. - Character strip : its descriptor gives the memory address of the character codes corresponding to the 1st displayed character. The characters and attributes (see code format III) are defined by a succession of codes stored in the RAM at addresses starting from the 1st one given by the descriptor. A character strip can be displayed or not by using the DE bit of its descriptor. A zoom can be made on it by using the ZY bit. Figure 6 : PWM Timing
PWM1 Signal V1[7:0] 0 TXTAL 256 . TXTAL
1
128 255
9/15
9425-08.AI
9425-07.AI
= 4 (min)
= 4n + 2
STV9425 - STV9425B - STV9426
FUNCTIONAL DESCRIPTION (continued) After the falling edge on V-SYNC, the first strip descriptor is read at the top of the current table of descriptors at the address given by P[9:0] (see DISPLAY CONTROL register).I f it is a spacing strip, SL[7:0] black or transparent scan lines are displayed. If it is a character strip, during CH[5:0] x (I + ZY) scan lines (CH[5:0] given by the CHARACTER HEIGHT register), the character codes are read at the addressesstarting from the 1st one given by the descriptor until a end of line character or the end of the scan line. The next descriptor is then read and the same process is repeated until the next falling edge on V-SYNC.
Figure 7 : Relation between Screen/Address Page/Character Code in RAM
DISP LAY CONTROL Re giste r CS D FBK FL[1:0] P8 P7 P8 V-SYNC
TOP SP ACING S TRIP 2nd CHARACTER S TRIP CODES OTHER TABLE OF DES CRIPTORS OTHER (UDC for e xa mple) 1st CHARACTE R S TRIP CODES 3rd CHARACTER S RTIP CODES OTHER (CODES OR DES CRIPTORS ) RAM CODE AND DES CRIPTORS SP ACING 1s t CHARACTER S TRIP ROW1 2n d CHARACTER S TRIP ROW2 S P ACING S TRIP SP ACING 3rd CHARACTER S TRIP ROW3 | BOTTOM S P ACING S TRIP SP ACING TABLE OF THE DES CRIPTORS S CREEN
Figure 8 : User Definable Character
ON THE SCREEN 36 Pixels (= 3 Characters) 1 2 3 Character Number
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18
IN THE RAM (example for Character n5)
Slice 0 Slice 1 Slice 2 Slice 3 Slice 4 Slice 5 Slice 6 Slice 7 Slice 8 Slice 9 Slice 10 Slice 11 Slice 12 Slice 13 Slice 14 Slice 15 Slice 16 Slice 17 Slice 18
: 0x01 : : : : : : : : : : : : : : : : : : 0x00 0x08 0x0c 0x0e 0x0f 0x0f 0x0f 0x0f 0x0e 0x0c 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 Odd Address
0xff = Slice 18 of the character n2 only for vertical shadowing (not displayed). 0xff 0x7f 0x3f 0x1f 0x1f 0x1f 0x1e 0x1e 0x3c 0x3c 0x78 0x78 0xf1 0x00 0x00 0x00 0x00 0x00 Even Address
36 Slices (= 2 Characters)
4
5
6
Character Number
10/15
9425-10.AI
9425-09.EPS
STV9425 - STV9425B - STV9426
FUNCTIONAL DESCRIPTION (continued) Table 1 : ROM Character Generator
CHARACTER NUMBER C(6:0) C(6:4) C(3:0)
0
0
1
2
3
4
5
6
7
1
2
3
4
5
6
7
8
9
a
b
c
d
e
f
11/15
9425-11.EPS
STV9425 - STV9425B - STV9426
FUNCTIONAL DESCRIPTION (continued) VI - User Definable Character The STV9425/25B/26 allows the user to dynamically define character(s) for his own needs (for a special LOGO for example). Like the ROM characters, a UDC is made of a 12 pixels x 18 slices dot matrix, but one more slice is added for the vertical shadowing when several UDCs are gathered to make a special great character (see Figure 8). In a UDC, each pixel is defined with a bit, 1 refers to foreground, and 0 to background color. Each slice of a UDC uses 2 bytes :
add + 1 add (even) PX11 PX10 PX9 PX8
The second PLL, full digital (see Figure 10), provides a pixel frequency locked on the horizontal synchro signal. The ratio between the frequencies of these 2 signals is : M = 12 x (LD[5:0] + 1) Where LD[5:0] is the value of the LINE DURATION register. Figure 10 : Digital PLL
M . FH-SYNC N . FXTAL %D %M FH-SYNC
9425-13.AI
PX7 PX6 PX5 PX4 PX3 PX2 PX1 PX0
D(n)
ALGO
err(n)
PX11is the left most pixel. Character slice address : SLICEADDRESS = 38 x (CHARACTER NUMBER) + (SLICE NUMBER). Where : - CHARACTER NUMBER is the number given by the character code, - SLICE NUMBER is the number given by the slice interpolator (n of the current slice of the strip : 1 < <18) VII - ROM Character Generator The STV9425/25B/26 includes a ROM character generator which is made of 128 alphanumeric or graphic characters (see Table 1) VIII - PLL The PLL function of the STV9425/25B/26provides the internal pixel clock locked on the horizontal synchro signal and used by the display processor to generate the R, G, B and fast blancking signals. It is made of 2 PLLs. The first one analogic (see Figure 9), provides a high frequency signal locked on the crystal frequency. The frequency multiplier is given by : N = 2 (FM[3:0] + 3) Where FM[3:0] is the value of the FREQUENCY MULTIPLIER register. Figure 9 : Analogic PLL
N . FXTAL VCO %N FXTAL
VIII.1 - Programming of the PLL Registers Frequency Multiplier (@3FF7) This register gives the ratio between the crystal frequency and the high frequency of the signal used by the 2nd PLL to provide, by division, the pixel clock. The value of this high frequency must be near to 200MHz (for example if the crystal is a 8MHz, the value of FM must be equal to 10) and greater than 6 x (pixel frequency). Initial Pixel Period (@3FF6) This register allows to increase the speed of the convergence of the PLL when the horizontal frequency changes (new graphic standart). The relationshipbetween FM[3:0], PP[7:0],LD[5:0],FHSYNC and FXTAL is :
2 (FM[3:0] + 3) FXTAL PP[7:0] = round 8 - 24 12 (LD[5:0] + 1) F HSYNC
FILTRE
12/15
9425-12.AI
Locking Condition Time Constant (@ 3FF4) This register gives the constants AS[2:0] and BS[2:0]used by the algo partof the PLL(see Figure 10) to calculate, from the phase error, err(n), the new value, D(n), of the division of the high frequency signal to provide the pixel clock. These two constants are used only in locking condition, which is true, if the phase error is less than a fixed value during at least, 4 scan lines. If the phase error becomes greater than the fixed value, the PLL is not in locking condition but in capture process. In this case, the algo part of the PLL used the other constants, AF[2:0] and BF[2:0], given by the next register. Capture Process Time Constant (@ 3FF5) The choice between these two time constants (locking condition or capture process) allows to decreasethe capture processtime by changingthe time response of the PLL.
STV9425 - STV9425B - STV9426
FUNCTIONAL DESCRIPTION (continued) VIII.2 - How to choose the value of the time constant ? The time response of the PLL is given by its characteristic equation which is : (x - 1)2 + ( + ) (x - 1) + = 0. Where : = 3 LD[5:0] 2A - 11 and = 3 LD[5:0] 2B - 19. (LD[5:0] = value of the LINE DURATION register, A = value of the 1st time constant, AF or AS and B = value of the 2d time constant, BF or BS). As you can see, the solution depend only on the LINE DURATION and the TIME CONSTANTS given by the I2C registers. If ( + )2 - 4 0 and 2 - < 4, the PLL is stable and its response is like this presented on Figure 11. Figure 11 : Time Response of the PLL/Characteristic Equation Solutions (with Real Solutions)
PLL Frequency f1 f0 Input Frequency
9425-14.AI
In this case the PLL is stable if > 0.7 damping coefficient). Figure 12 : Time Response of the PLL/Characteristic Equation Solutions (with Complex Solutions)
PLL Frequency f1 f0 Input Frequency
9425-15.AI
t
f1 f0 t
The Table 2 gives some good values for A and B constants for different values of the LINE DURATION. Summary For a good working of the PLL : - A and B time constants must be chosen among values for which the PLL is stable, - B must be equal or greater than A and the difference between them must be less than 3, - The greater (A, B) are, the faster the capture is. An optimalchoice for the most of applicationsmight be : - For locking condition : AS = 0 and BS = 1, - For capture process : AS = 2 and BS = 4. But for each application the time constants can be calculated by solving the characteristic equation and choosing the best response.
t
f1 f0 t
If ( + )2 - 4 0, the response of the PLL is like this presented on Figure 12. Table 2 : Valid Time Constants Examples
B\A 0 1 2 3 4 5 6 7 0 YYYY YYYY NYYY NNNY NNNN NNNN NNNN NNNN 1 YYYY YYYY YYYY YYYY (1) NYYY NNNY NNNN NNNN 2 YYYY YYYY YYYY YYYY YYYY YYYY NYYY NNNY
Note : 1. Case of A[2:0] = 1 (001) and B[2:0] = 4 (100) : LD Valid Time Constants 16 N 32 Y 48 Y 63 Y Value of LINE DURATION Register (@ 3FF0) : LD = 16 : LD[5:0] = 010000 LD = 32 : LD[5:0] = 100000 LD = 48 : LD[5:0] = 110000 LD = 63 : LD[5:0] = 111111 Table meaning : N = No possible capture Y = PLL can lock
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9425-05.TBL
3 YYYN YYYN YYYN YYYN YYYN YYYN YYYN YYYN
4 YNNN YNNN YNNN YNNN YNNN YNNN YNNN YNNN
5 NNNN NNNN NNNN NNNN NNNN NNNN NNNN NNNN
6 NNNN NNNN NNNN NNNN NNNN NNNN NNNN NNNN
STV9425 - STV9425B - STV9426
PACKAGE MECHANICAL DATA (STV9425 - STV9425B) 24 PINS - PLASTIC SHRINK DIP
E E1
A1 B B1 e
A2
Stand-off e1 e2
L c D E 24 13 F
.015 0,38 Gage Plan e
A
1
12 e3
SDIP24
e2
Dimensions A A1 B B1 C D E E1 e e1 e2 e3 L
Min. 0.51 3.05 0.36 0.76 0.23 22.61 7.62 6.10
Millimeters Typ.
Max. 5.08 4.57 0.56 1.14 0.38 23.11 8.64 6.86
Min. 0.020 0.120 0.0142 0.030 0.0090 0.890 0.30 0.240
Inches Typ.
Max. 0.20 0.180 0.0220 0.045 0.0150 0.910 0.340 0270
3.30 0.46 1.02 0.25 22.86 6.40 1.778 7.62
0.130 0.0181 0.040 0.0098 0.90 0.252 0.070 0.30
2.54
3.30
0.10
0.130
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SDIP24.TBL
10.92 1.52 3.81
0.430 0.060 0.150
PMSDIP24.EPS
STV9425 - STV9425B - STV9426
PACKAGE MECHANICAL DATA (STV9426) 16 PINS - PLASTIC DIP
Dimensions a1 B b b1 D E e e3 F I L Z
Min. 0.51 0.77
Millimeters Typ.
Max. 1.65
Min. 0.020 0.030
Inches Typ.
Max. 0.065
0.5 0.25 20 8.5 2.54 17.78 7.1 5.1 3.3 1.27
0.020 0.010 0.787 0.335 0.100 0.700 0.280 0.201 0.130 0.050
DIP16.TBL
Information furni shed is believed to be accurate and reliable. However, SGS-THOMSON Micr oelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No licence is granted by implication or otherwise und erany patent or patent rights of SGS-THOMSON Microelectronics. Specifications mentioned in this publication are subject to change without notice. This pu blication supersedes and replaces all information previously supplied. SGS-THOMSON Microelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of SGS-THOMSON Microelectronics. (c) 1997 SGS-THOMSON Microelectronics - All Rights Reserved Purchase of I 2C Components of SGS-THOMSON Microelectronics, conveys a license under the Philips 2 2 I C Patent. Rights to use these components in a I C system, is granted provided that the system conforms to the I2C Standard Specifications as defined by Philips. SGS-THOMSON Microelectronics GROUP OF COMPANIES Australia - Brazil - Canada - China - France - Germany - Italy - Japan - Korea - Malaysia - Malta - Morocco The Netherlands - Singapore - Spain - Sweden - Switzerland - Taiwan - Thailand - United Kingdom - U.S.A.
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PM-DIP16.EPS

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